Integrated circuits are typically very complex and require numerous iterations of design and verification at different levels of abstraction. The levels of abstraction can be differentiated by the environmental influences and physical implementation details modeled.
Some environmental influences may create timing anomalies that affect the timing of received signals. Even if accurate circuit models are used to account for various elements of delay associated with individual circuit elements, the delays are expected to be deterministic. Other sources of delay may be present in the system. Typical simulators do not account for varying delays in a common clock signal that might be the result of physical phenomenon such as jitter.
Jitter can have deterministic as well as non-deterministic effects on a clock. Jitter can vary across the integrated circuit such that the change in the received clock is different at distinct physical locations. This variation in the clock can create race conditions resulting in unexpected logical behavior. Such race conditions are detrimental to the planned operation of the integrated circuit.
Despite attempts to minimize the effects of jitter during the design phase, some physical embodiments of the integrated circuit may suffer from an unacceptable amount of jitter. Testing may be performed on the integrated circuit to determine whether the integrated circuit is behaving as expected and whether any unexpected behavior is the result of jitter. In view of the size and complexity of modern integrated circuits, however, such testing may be impractical for quick verification.